1. Technical Field
The present disclosure relates to systems having processors, and more particularly, to a processor system and method for reducing power consumption in an idle mode.
2. Discussion of Related Art
In a processing device, power consumption of a processor accounts for a large portion of the entire power consumption of the device. The portion of power consumption attributable to the processor increases with operation speed. High performance processors having reduced power needs are important for portable electric devices operated by battery such as cell phones, PDA (Personal Digital Assistant), digital cameras, notebooks, etc.
One scheme for reducing the power consumption of a processor includes support for various operation modes according to an operation of the processor. An example of an operation mode is an idle mode. Processors include a CPU (Central Processing Unit) and other hardware modules. Each module is operated in synchronization with a clock signal generated by a clock source. In the idle mode, the CPU is not operated. Idle mode does not affect an operation state of peripheral devices (e.g., an input/output control part, another hardware module such as a memory). The idle mode is maintained until the CPU is operated again by events such as interrupts or timers. During the idle mode, the frequency of a clock signal supplied to CPU may be reduced, or a clock may be disconnected from the CPU.
The idle mode results in reduced power consumption due to the CPU being idle. The CPU can be awoken from the idle mode by an interrupt request.
Power consumption of a CMOS (Complementary Metal-Oxide Semiconductor) CPU may be determined according to the following:
                                                                        P                avg                            =                            ⁢                                                P                  switch                                +                                  P                                      short                    ⁢                                          -                                        ⁢                    circuit                                                  +                                  P                  leakage                                +                                  P                  static                                                                                                        =                            ⁢                                                                    a                                          0                      →                      1                                                        ⁢                                      C                    L                                    ⁢                                      VV                    DD                                    ⁢                                      f                    clk                                                  +                                                      I                    SC                                    ⁢                                      V                    DD                                                  +                                  I                  leakage                                +                                  I                  static                                +                                  V                  DD                                                                                        [                  Eq          .                                          ⁢          1                ]            
A unit element of the CMOS comprises two complementary transistors, including a PMOS transistor and a NMOS transistor. In Eq. 1, Pswitch represents power consumption when a transistor is switched, Pshort-circuit represents power consumption when the NMOS transistor and the PMOS transistor are simultaneously connected, Pleakage represents power consumption by leakage current, and Pstatic represents continuous power consumption of a transmission gate or a bias circuit. And, where, α0→1 represents a probability of a signal level of an input/output node of the CMOS element being transitioned from 0 to 1, CL represents capacitance, V represents a voltage of an input node, VDD represents power voltage and ƒclk represents a frequency of a clock signal supplied to CPU.
In accordance with Eq. 1, during the idle mode, switch power Pswitch is reduced, but power consumption of other modules continues as before.